The physical design starts with the creation of a new partition per Tx/Rx antenna path. In the system's hierarchy, each Tx/Rx data path is a single design partition assigned to a pre-allocated LogicLock region. The Design Partition and the LogicLock tools in Quartus II realize these floor planning rules in an efficient and reusable manner. The radio head floorplan consists of 8 rectangular-shaped, mutually exclusive "stripy" regions, stretching from the left side of the targeted chip to the right. The fitter tool will have to solve 8 almost identical sub regions, one per antenna's data path. Four RX/TX circuits will be located above the ARM processors, and four below.
Further, the FPGA's dual core ARM A9 processing subsystem is centered in the middle of the FPGA, dividing the programmable logic areas into and upper and lower regions. The horizontal limit of these 8 parallel data paths can balance the distance between each data path and the left vertical end-side of the chip, where the transceivers lie. The chosen FPGA, the Arria 10 10AX066 (660 kLE), has the CPRI and JESD204B transceivers on the left hand side of the chip Therefore, each antenna's Tx/Rx path "folds" across the horizontal dimensions of the chip forming a mirrored "C" shape, due to the fact that all its input and output interfaces are placed on the left side. This will require eight identical CPRI to JEDS204B antenna paths. The goal is to implement 8 RX and 8 RX antenna systems, with two independent LTE channels for each antenna system. This allows for modular partitioning once the layout is determined for a single RX/TX antenna path, since any further antenna paths are functionally and logically identical.
Due to the support of many antennas, the floor planning method can effectively leverage both the homogeneity among the parallel data paths supporting each antenna and the design's granularity. When targeting modern wireless, this argument can be even taken a step further. That simplifies the physical design task, allowing the engineering design teams to largely focus on the characteristics and the logic requirements of the logic circuit. are already floor planned and fixed, location-wise. Fortunately, floor planning a custom logic design on a topology of a modern FPGA device such as the 20nm Arria 10 can be more straightforward than in custom IC design, inasmuch as the clock-tree and all the hard-logic components such as the IO transceivers, the PCI controllers, the DSP blocks, the RAM blocks etc. However, this changes for large FPGA designs requiring timing closure in the 500 MHz range. While being an essential step in IC design, floor planning has not been standardized in the FPGA compilation flow, especially if Fmax requirements can be met without resorting to floor planning. It is being widely used for decades in ASIC design integration. Traditionally, floor planning has been the first step in the common physical design flow of the IC design. However, larger designs may require leveraging the floor planning capabilities within Quartus II. These techniques are sufficient to achieve very high Fmax on moderate size designs.
#Dsp builder incremental compilation software
This allows the Quartus II place and route software greater latitude in placement, without compromising the overall design Fmax. Designers can also added "dummy" pipeline stages into the DSP Builder design between large modules, such as CFR & DPD for instance. A number of other DSP Builder optimizations for high Fmax designs are used, such as: to select the threshold setting to steer the tool towards use of ALM registers rather than MLABs for FIR filter input delay stages, or to set a threshold to force pipelining or large counters of many bits.